Designer-defect mediated clamping of ferroelectric domain walls for more stable nanoelectronics

Designer-defect mediated clamping of ferroelectric domain walls for more stable nanoelectronics
Co-author Dr Daniel Sando preparing materials for study at UNSW. Credit: FLEET

A UNSW study published today in Nature Communications presents an exciting step towards domain-wall nanoelectronics: a novel form of future electronics based on nano-scale conduction paths, and which could allow for extremely dense memory storage.

FLEET researchers at the UNSW School of Materials Science and Engineering have made an important step in solving the technology's primary long-standing challenge of information stability.

Domain walls are "atomically sharp" separating regions of uniform in .

Domain walls in ferroelectrics possess fascinating properties, and are considered separate entities with properties that are dramatically different from the parent bulk ferroic material.

These properties are brought about by changes in structure, symmetry and chemistry confined within the wall.

"This is the fundamental starting point underpinning wall nanoelectronics," says study author Prof Jan Seidel.

The "switching" property of ferroelectric materials makes them a popular candidate for low-voltage nanoelectronics. In a ferroelectric transistor, distinct polarization states would represent the computational zero and one states of binary systems.

However, the stability of that stored polarization information has proven to be a challenge in application of the technology to , especially for very small nanoscale domain sizes, which are desired for high storage densities.

Designer-defect mediated clamping of ferroelectric domain walls for more stable nanoelectronics
Ferroelectric materials can be considered the electrical equivalent of a permanent magnet, possessing a spontaneous polarisation. This polarisation is ‘switchable’ by an electric field. Credit: FLEET

"The polarization state in ferroelectric materials decays typically within days to a few weeks, which would mean information storage failure in any domain-wall data storage system," says author Prof Nagy Valanoor.

The period of time that information can be stored in ferroelectric materials, ie the stability of the stored polarization information, is thus a key performance feature.

To date, this long-standing issue of information instability has been one of the main limitations on the technology's application.

The study investigates the ferroelectric material BiFeO3 (BFO) with specially introduced designer defects in thin films. These designer defects can clamp down in the material, effectively preventing the ferroelectric domain relaxation process that drives information loss.

"We used a 'defect engineering' method to design and fabricate a special BFO thin film that is not susceptible to retention loss over time," says lead author Dr. Daniel Sando.

Pinning of domain walls is thus the main factor used to engineer very long polarization retention.

Designer-defect mediated clamping of ferroelectric domain walls for more stable nanoelectronics
Voltage-dependent domain formation. Credit: FLEET

"The novelty of this new research lies in precisely-controlled pinning of the domain wall, which allowed us to realize superior polarization retention," says lead author Dawei Zhang.

The research provides critical new thinking and concepts for domain-wall based nanoelectronics for non-volatile data and logic device architectures.

In addition the mixed phase BFO–LAO system is a fertile ground for other intriguing , including piezoelectric response, field-induced strain, electrochromic effects, magnetic moments, electrical conductivity and mechanical properties.

More information: Dawei Zhang et al. Superior polarization retention through engineered domain wall pinning, Nature Communications (2020). DOI: 10.1038/s41467-019-14250-7

Journal information: Nature Communications

Provided by FLEET

Citation: Designer-defect mediated clamping of ferroelectric domain walls for more stable nanoelectronics (2020, January 20) retrieved 28 March 2024 from https://phys.org/news/2020-01-designer-defect-clamping-ferroelectric-domain-walls.html
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